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 STP5NK100Z - STF5NK100Z STW5NK100Z
N-CHANNEL 1000V - 2.7 - 3.5A TO-220/TO-220FP/TO-247 Zener-Protected SuperMESHTMMOSFET
Table 1: General Features
TYPE STF5NK100Z STP5NK100Z STW5NK100Z
s s s s s s s
Figure 1: Package
ID 3.5 A (*) 3.5 A 3.5 A Pw 30 W 125 W 125 W
3 1 2
VDSS 1000 V 1000 V 1000 V
RDS(on) < 3.7 < 3.7 < 3.7
TYPICAL RDS(on) = 2.7 EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
TO-220
TO-220FP
3 2 1
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established stripbased PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
TO-247
Figure 2: Internal Schematic Diagram
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES
Table 2: Order Codes
SALES TYPE STF5NK100Z STP5NK100Z STW5NK100Z MARKING F5NK100Z P5NK100Z W15NK100Z PACKAGE TO-220FP TO-220 TO-247 PACKAGING TUBE TUBE TUBE
Rev. 2 October 2004 1/12
STP5NK100Z - STF5NK100Z - STW5NK100Z
Table 3: Absolute Maximum ratings
Symbol Parameter
STP5NK100Z STW5NK100Z
Value
STF5NK100Z
Unit
VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) VISO Tj Tstg
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Operating Junction Temperature Storage Temperature 3.5 2.2 14 125 1
1000 1000 30 3.5 (*) 2.2 (*) 14 (*) 30 0.24 4000 4.5 2500 -55 to 150 -55 to 150
V V V A A A W W/C V V/ns V C C
( ) Pulse width limited by safe operating area (1) ISD 3.5A, di/dt 200A/s, VDD V(BR)DSS, Tj TJMAX. (*) Limited only by maximum temperature allowed
Table 4: Thermal Data
TO-220 TO-247 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 1 62.5 300 TO-220FP 4.2 C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 3.5 250 Unit A mJ
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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STP5NK100Z - STF5NK100Z - STW5NK100Z
ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On /Off
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125C VGS = 20 V VDS = VGS, ID = 100 A VGS = 10 V, ID = 1.75 A 3 3.75 2.7 Min. 1000 1 50 10 4.5 3.7 Typ. Max. Unit V A A A V
IGSS VGS(th) RDS(on)
Table 8: Dynamic
Symbol gfs (1) Ciss Coss Crss Coss eq (3). td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V , ID = 1.75 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 4 1154 106 21.3 46.8 22.5 7.7 51.5 19 42 7.3 21.7 59 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
Equivalent Output Capacitance VGS = 0 V, VDS = 0 to 800 V Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 500 V, ID = 1.75 A, RG = 4.7 , VGS = 10 V (see Figure 21) VDD = 800 V, ID = 3.5 A, VGS = 10 V (see Figure 24)
Table 9: Source Drain Diode
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3.5 A, VGS = 0 ISD = 3.5 A, di/dt = 100 A/s VDD = 35V (see Figure 22) ISD = 3.5 A, di/dt = 100 A/s VDD = 35V, Tj = 150C (see Figure 22) 605 3.09 10.5 742 4.2 11.2 Test Conditions Min. Typ. Max. 3.5 14 1.6 Unit A A V ns C A ns C A
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. (3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
3/12
STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 3: Safe Operating Area For TO-220 Figure 6: Thermal Impedance TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Safe Operating Area For TO-247
Figure 8: Thermal Impedance For TO-247
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 9: Output Characteristics Figure 12: Transfer Characteristics
Figure 10: Transconductance
Figure 13: Static Drain-Source On Resistance
Figure 11: Gate Charge vs Gate-source Voltage
Figure 14: Capacitance Variations
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 15: Normalized Gate Threshold Voltage vs Temperature Figure 18: Normalized On Resistance vs Temperature
Figure 16: Source-Drain Forward Characteristics
Figure 19: Normalized BVDSS vs Temperature
Figure 17: Maximum Avalanche Energy vs Temperature
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 20: Unclamped Inductive Load Test Circuit Figure 23: Unclamped Inductive Wafeform
Figure 21: Switching Times Test Circuit For Resistive Load
Figure 24: Gate Charge Test Circuit
Figure 22: Test Circuit For Inductive Load Switching and Diode Recovery Times
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STP5NK100Z - STF5NK100Z - STW5NK100Z
TO-220 MECHANICAL DATA
DIM. A b b1 c D E e e1 F H1 J1 L L1 L20 L30 mm. MIN. 4.40 0.61 1.15 0.49 15.25 10 2.40 4.95 1.23 6.20 2.40 13 3.50 16.40 28.90 3.75 2.65 3.85 2.95 0.147 0.104 TYP MAX. 4.60 0.88 1.70 0.70 15.75 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 MIN. 0.173 0.024 0.045 0.019 0.60 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 0.645 1.137 0.151 0.116 inch TYP. MAX. 0.181 0.034 0.066 0.027 0.620 0.409 0.106 0.202 0.052 0.256 0.107 0.551 0.154
oP
Q
8/12
STP5NK100Z - STF5NK100Z - STW5NK100Z
TO-220FP MECHANICAL DATA
mm. MIN. 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 28.6 9.8 2.9 15.9 9 3 30.6 10.6 3.6 16.4 9.3 3.2 1.126 .0385 0.114 0.626 0.354 0.118 TYP MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.141 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409
DIM. A B D E F F1 F2 G G1 H L2 L3 L4 L5 L6 L7 O
A
B
L3 L6 L7
F1 F
D
G1 H
F2
L2 L5
E
123
L4
G
9/12
STP5NK100Z - STF5NK100Z - STW5NK100Z
TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
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STP5NK100Z - STF5NK100Z - STW5NK100Z
Table 10: Revision History
Date 27-Sep-2004 08-Oct-2004 Revision 1 2 First release. Final datasheet Description of Changes
11/12
STP5NK100Z - STF5NK100Z - STW5NK100Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
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